With the growing popularity and complexity of very large scale integration (VLSI) designs, traditional test techniques, such as bed of nails tests and card edge tests provide limited visibility into internal VLSI machine states. Moreover, bed of nails tests and card edge tests are limited to a manufacturing environment and provide no assistance in evaluating the functionality of a VLSI device operating in an installed electronic assembly. As a result, insight into internal machine states of a VLSI device is gained through scan testing or automatic test program generation (ATPG).
The use of scan testing or ATPG enables observation of internal machine states of a VLSI device. Although scan test circuitry is designed and built into the VLSI device, there are logical gate assemblies and circuits that do not adapt well to conventional scan testing or ATPG methods. Typically, the addition of conventional scan circuitry causes additional gate delay in the logical gate assembly. One such logical gate assembly that does not adapt well to conventional scan testing methods and circuitry is a dynamic latch, sometimes referred to as a glitch catcher. As such, given that device-operating speed is a significant measure of a component value, conventional scan testing of dynamic sequential devices provides an undue burden to VLSI designs and devices.